This speed 4-bit Arithmetic Logic Unit (ALU).

This
paper presents the design of high speed 4-bit Arithmetic Logic Unit (ALU). ALU is
one of the most important parts of a processor which is designed to perform the
arithmetic and logic operations. The two important features are considered for
designing an ALU are increasing the speed and reducing power consumption. The
overall performance of the system will depend on the speed of the different
modules used in the design. However increasing the performance of ALU also
increases the power consumption. To achieve the low power consumption, high
speed ALU is proposed using 1-bit hybrid full adder. The performance of proposed
ALU is verified using Tanner EDA V13 with CMOS technology of 0.25µm. The
simulated results show that the proposed design reduces the number of transistors
that will result in lesser area occupation and reduces the power consumption
comparing with the existing ALU’s.

Key terms
: ALU, Hybrid adder, power consumption,
Tanner.

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I.                    
INTRODUCTION

Portable devices such as mobile phones,
notebooks, laptops etc. use batteries for their operations. The most important
feature of modern electronics is low power and energy efficient active block
that set up the implementation of all devices that are operated by battery. In
a modern electronics, designing of accurate and fast arithmetic circuit which
leads to long lasting battery operated designs. Arithmetic circuits are the
significant building block in Very Large Scale Integrated (VLSI) circuits and
efficient implementation of these circuits will enhance the performance of the
entire system. The Arithmetic Logic Unit (ALU)
implements
the basic arithmetic and logical operation. ALU
is a fundamental component of all CPU and it is an integral part of the execution
unit. CPU can be more powerful, but it also can
consume more energy and creates more heat depending on how the ALU is designed. Therefore, it is important to
balance between power consumption, speed and complexity of the ALU. At high speed, the CPU consumes more power and
power dissipation is high. There are many different power reducing techniques
being used to design low power, high-performance chips based on Complementary
Metal-Oxide-Semiconductor (CMOS)
such as reducing voltage, load capacitance or switching frequency of the output
node. By reducing the supply voltage (Vdd), the power consumption is
minimized which results in quadratic improvement in the power dissipation of a CMOS circuit.